Many people are
looking for an engineering career while having an edge to the creativity inside.
One can have a career in engineering while keeping the artist inside of them
active. The best option for such people is to shape a career with VLSI.
VLSI Engineer is about the science and
art of designing complex and large electronic systems on a chip which is
usually very small. A physical design
engineer has to design a circuit while keeping in mind the geometric
designs for the printing to be as intricate as possible on silicon. It also requires one to have the best
engineering skills to implement the designs
Skills
and challenges faced by VLSI Design Engineers:
In order to
verify a VLSI physical design Engineer,
it is important to get the performance as well as the functionality of the
design, keeping in view the specifications that one is looking for. There is a verification Engineer who needs
to design and create an environment which is suitable for verifying the design
often referred to as verification environment. The verification environment is
supposed to mimic and act like a real-world
scenario to carefully analyze the design
which is also known as Verification Intellectual Property (VIP) for every
design which is under rest and is capable of capturing the failure models of
the design.
There are two different types of
verification processes used for the same. They are as under:
1. Functional
Verification of the system: It is important to analyze
and examine if the design is as according to the specification and it is very
important to test if the design is able to
do what it is designed to do ( as per the requirement ).
2. Verification
of the timing: There is a specific clock time which is kept, and it is important
to see if the design is fast enough to run without showing any error at which
the clock is targeted. Static Timing
Analysis (STA) is a method which is used to compute the expected time of a
digital circuit without having to require the stimulation.
3. Dynamic
Timing Stimulation of the system: It is referred to as the verification of the
ASCI system to be fast enough to run in a specific time frame without generating
any error. All of this is accomplished by
the stimulation of the design used in the synthetization
of the Integrated Circuit. This testing is in contrast with the static timing analyzer which has a very similar goal except
that it does not require the real
functionality of the Integrated Circuit.
One of the major challenges of the VLSI Engineer is that they
can seldom be wrong and have a choice of being incorrect after investing so
much of money in fabrication, designing and testing which sometimes go to
certain billion USD. An error generated after completing a design can cost the
entire organization a lot of money which
keep no room for a VLSI Engineer to make a
mistake.
